Diseño de compuertas lógicas cuaternarias CMOS en modo voltaje
Algebra of multiple logical values emerged as a solution to the problems present in binary circuits (2 logical levels): misuse of area and power in digital integrated circuits. Among the possible alternatives, several proposals for quaternary algebras (4 logical levels) have been presented, together...
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2021
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| author | Galindo Rodríguez, María José |
| author2 | Duarte Gonzáles, Mario Enrrique |
| author_facet | Duarte Gonzáles, Mario Enrrique Galindo Rodríguez, María José |
| author_sort | Galindo Rodríguez, María José |
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| description | Algebra of multiple logical values emerged as a solution to the problems present in binary circuits (2 logical levels): misuse of area and power in digital integrated circuits. Among the possible alternatives, several proposals for quaternary algebras (4 logical levels) have been presented, together with their corresponding logical operators (gates); which have been designed and implemented in both current and voltage modes, using CMOS technology. The best configuration for logic gates is in voltage mode because there is less power dissipation, as reported in the literature. In this work, a design was proposed for the circuits of the quaternary gates implementing CMOS technology in voltage mode with a smaller required area than the gates reported in recent works, the correct operation of the circuits was verified using the CADENCE Virtuoso program, as well as, the electrical characteristics: slew rate and power, by means of simulation. Finally, to evaluate the correct operation of the circuits, a quaternary demultiplexer was designed, built and simulated with the same tool. |
| format | Trabajo de grado (Pregrado y/o Especialización) |
| id | repositorio.uan.edu.co-123456789-2213 |
| institution | Repositorio Digital UAN |
| language | spa |
| publishDate | 2021 |
| publisher | Universidad Antonio Nariño |
| record_format | dspace |
| spelling | repositorio.uan.edu.co-123456789-22132024-10-09T22:55:50Z Diseño de compuertas lógicas cuaternarias CMOS en modo voltaje Galindo Rodríguez, María José Duarte Gonzáles, Mario Enrrique Algebra de multiples valores lógicos. Algebra of multiple logical values. Algebra of multiple logical values emerged as a solution to the problems present in binary circuits (2 logical levels): misuse of area and power in digital integrated circuits. Among the possible alternatives, several proposals for quaternary algebras (4 logical levels) have been presented, together with their corresponding logical operators (gates); which have been designed and implemented in both current and voltage modes, using CMOS technology. The best configuration for logic gates is in voltage mode because there is less power dissipation, as reported in the literature. In this work, a design was proposed for the circuits of the quaternary gates implementing CMOS technology in voltage mode with a smaller required area than the gates reported in recent works, the correct operation of the circuits was verified using the CADENCE Virtuoso program, as well as, the electrical characteristics: slew rate and power, by means of simulation. Finally, to evaluate the correct operation of the circuits, a quaternary demultiplexer was designed, built and simulated with the same tool. El álgebra de múltiples valores lógicos surgió como una solución a los problemas presentes en los circuitos binarios (2 niveles lógicos): mal uso de área y potencia en circuitos integrados digitales. Entre las posibles alternativas se han presentado varias propuestas de álgebras cuaternarias (4 niveles lógicos), junto con sus correspondientes operadores (compuertas) lógicos; los cuales han sido diseñadas e implementadas tanto en modo corriente como en modo voltaje, utilizando tecnología CMOS. La mejor configuración para la compuertas lógicas es en modo voltaje debido que hay una menor disipación de potencia, tal como se ha reportado en la literatura. En este trabajo, se propuso un diseño para los circuitos de las compuertas cuaternarias implementando tecnología CMOS en modo voltaje con área requerida menor que las compuertas reportadas en trabajos recientes, se verificó el correcto funcionamiento de los circuito utilizando el programa CADENCE Virtuoso, así como, las características eléctricas: slew rate y potencia, por medio de simulación. Por último, para evaluar el funcionamiento correcto de los circuitos se diseñó, construyó y simuló con la misma herramienta un demultiplexor cuaternario. Otro Ingeniero(a) Electrónico(a) Pregrado Costo total del proyecto $3’503.182. Financiación propia $1’635.000. Financiación UAN $980.000 Presencial 2021-03-02T14:20:56Z 2021-03-02T14:20:56Z 2020-07-21 Trabajo de grado (Pregrado y/o Especialización) info:eu-repo/semantics/acceptedVersion http://purl.org/coar/resource_type/c_7a1f http://purl.org/coar/version/c_970fb48d4fbd8a85 http://repositorio.uan.edu.co/handle/123456789/2213 PhD W. Merlijn van Spengen. High voltage amplifiers: how fast are they really?, March2016. Wikipedia. Puerta not — wikipedia, la enciclopedia libre, 2020. [Internet; descargado 16-julio-2020]. ME Romero Romero, E Mazina Martins, DCA Arigoni, A de M Nogueira, and ME Duarte-González. Voltage cmos quaternary gates for digital designs. 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Proceedings., pages 207–212, 2003. Z. Zilic and Z. G. Vranesic. Multiple-valued logic in fpgas. In Proceedings of 36th Midwest Symposium on Circuits and Systems, pages 1553–1556 vol.2, 1993. M. H. A. Khan. Quaternary quantum algorithm for determining properties of quaternary logic function. In 14th International Conference on Computer and Information Technology (ICCIT 2011), pages 1–5, 2011. M. H. A. Khan. Synthesis of incompletely specified multi-output quaternary function using quaternary quantum gates. In 2007 10th international conference on computer and information technology, pages 1–6, 2007. K. M. Ishtiak, Safayat-Al-Imam, and N. A. Mahmud. Design and embodiment of larger quaternary multiplexer and demultiplexer. In 2014 International Conference on Electrical Engineering and Information Communication Technology, pages 1–5, 2014. S. Hajare and P. Dakhole. Design of adders with quaternary logic. In 2015 International Conference on Industrial Instrumentation and Control (ICIC), pages 599–601, 2015. M. S. E. Sendi, A. Khorami, S. Kananian, M. Sharifkhani, and A. M. Sodagar. Lowpower cmos voltage-mode quaternary latched comparator. In 2015 23rd Iranian Conference on Electrical Engineering, pages 1083–1088, 2015. M. S. E. Sendi, M. Sharifkhani, and A. M. Sodagar. Cmos-compatible structure for voltage-mode multiple-valued logic circuits. In 2011 18th IEEE International Conference on Electronics, Circuits, and Systems, pages 438–441, 2011. Wu Haixia, Zhong Shunan, Sun Zhentao, Qu Xiaonan, and Chen Yueyang. Design of low-power quaternary flip-flop based on dynamic source-coupled logic. In 2011 International Conference on Electronics, Communications and Control (ICECC), pages 826–828. IEEE, 2011. Evandro Mazina Martins and Milton Ernesto Romero Romero. Voltage mode multiple valued analog to quaternary mapping. IEEE Latin America Transactions, 16(3):792– 798, 2018. Mohammad S Eslampanah Sendi, Mohammad Sharifkhani, and Amir M Sodagar. Cmoscompatible structure for voltage-mode multiple-valued logic circuits. In 2011 18th IEEE International Conference on Electronics, Circuits, and Systems, pages 438–441. IEEE, 2011. Enrique Mandado Pérez, Enrique Mandado, and Yago Mandado. Sistemas electrónicos digitales. Marcombo, 2007. Wikipedia. Electrónica digital — wikipedia, la enciclopedia libre, 2019. [Internet; descargado 27-junio-2020]. Wikipedia. Circuito digital — wikipedia, la enciclopedia libre, 2020. [Internet; descargado 12-julio-2020]. Wikipedia. Código binario — wikipedia, la enciclopedia libre, 2020. [Internet; descargado 27-junio-2020]. Wikipedia. Algebra de boole — wikipedia, la enciclopedia libre, 2020. [Internet; descargado 27-junio-2020]. MARIO ENRIQUE DUARTE GONZALEZ. Projeto e implementaC ,Ao dos operadores lógicos para a Álgebra de múltiplos valores. Master’s thesis, UNIVERSIDADE ´ FEDERAL DE MATO GROSSO DO SUL, 2011. G. Prasad and R. Kusuma. Statistical (m-c) and static noise margin analysis of the sram cells. In 2013 Students Conference on Engineering and Systems (SCES), page 1, 2013. instname:Universidad Antonio Nariño reponame:Repositorio Institucional UAN repourl:https://repositorio.uan.edu.co/ spa Acceso abierto Attribution-NonCommercial-NoDerivatives 4.0 International (CC BY-NC-ND 4.0) https://creativecommons.org/licenses/by-nc-nd/4.0/ info:eu-repo/semantics/openAccess http://purl.org/coar/access_right/c_abf2 image/jpeg application/pdf Universidad Antonio Nariño Ingeniería Electrónica Facultad de Ingeniería Mecánica, Electrónica y Biomédica Bogotá - Sur |
| spellingShingle | Algebra de multiples valores lógicos. Algebra of multiple logical values. Galindo Rodríguez, María José Diseño de compuertas lógicas cuaternarias CMOS en modo voltaje |
| title | Diseño de compuertas lógicas cuaternarias CMOS en modo voltaje |
| title_full | Diseño de compuertas lógicas cuaternarias CMOS en modo voltaje |
| title_fullStr | Diseño de compuertas lógicas cuaternarias CMOS en modo voltaje |
| title_full_unstemmed | Diseño de compuertas lógicas cuaternarias CMOS en modo voltaje |
| title_short | Diseño de compuertas lógicas cuaternarias CMOS en modo voltaje |
| title_sort | diseno de compuertas logicas cuaternarias cmos en modo voltaje |
| topic | Algebra de multiples valores lógicos. Algebra of multiple logical values. |
| url | http://repositorio.uan.edu.co/handle/123456789/2213 |
| work_keys_str_mv | AT galindorodriguezmariajose disenodecompuertaslogicascuaternariascmosenmodovoltaje |
